A charge trapping memory cell comprises a channel region between regions of source and drain, above which a gate electrode is arranged. A storage layer sequence, which usually contains a nitride layer between boundary layers made of oxide, is situated as gate dielectric between the channel region and the gate electrode. Hot electrons from the channel (channel hot electrons, CHE) are trapped in the storage layer during the programming of the charge trapping memory cell. The electrons in the channel are accelerated from source to drain in order to program a bit in the storage layer made of nitride above the drain region. If the polarity of the electrical voltage applied between source and drain for this purpose is reversed, a bit can likewise be programmed in the storage layer above the source region. In this way, it is possible to store two bits of information in each of these memory cells. The electrons remain localized in the nitride layer, so that the memory cell is nonvolatile.
In order to erase the memory cell, the charge present in the storage layer is compensated for by hot holes injected into the storage layer from the channel. In this case, the problem arises that owing to the different mobilities and masses of the different charge carriers, the distributions of the electrons and holes in the storage layer do not correspond after the erasure process. The position of the holes is concentrated to a greater extent, and the center thereof is displaced somewhat with respect to the center of the electron distribution. As a result, the number of possible programming/erasure cycles is considerably reduced.
If, instead of injecting hot holes into the storage layer, provision is made for forcing the electrons back from the storage layer into the channel region or to source or drain, a negative potential must be applied to the gate electrode. This makes it necessary for the drive circuit alternately to supply both positive and negative potentials for the gate electrode. A reversal of the charge carriers used, so that the programming is performed using hot holes and the erasure is performed using electrons injected from the channel, does not solve the problem either, owing to a lack of reliability due to defect sites produced by the hot holes.
Since, when using electrons for programming and hot holes for erasure, apart from the generation of a permanent electrical dipole, a complete compensation of the charges is not possible and the erasure process is therefore increasingly impaired, it is necessary, in order to increase the durability and reliability of the memory cell, to adapt the applied voltages in each case to the changed conditions as the number of programming/erasure cycles increases. However, this is possible only to a certain extent until finally the operating conditions become unsuitable on account of the required compensation for operation of the memory cell with this circuit.